Job Description: As a senior member of design verification team, your responsibilities will include：

• Design and implement verification infrastructure and platforms
• Develop, test and support UVM testbenches for SoC level/ module level verification
• Develop verification plans from design document, review and execute verification plans
• Verify various features using targeted/random/cornercase/coverage tests
• Code/functional coverage analysis, and devise strategy to fill coverage holes
• Develop, test and support scripts for simulation, regression management Job

• Solid understanding of verification methodology including System Verilog/UVM/SVA
• Hands-on expertise in UVM infrastructure development and testbench design
• Experience with the full verification lifecycle including block/full-chip/gate-level/low power verification and code/functional coverage analysis
• Design knowledge of one or more of industry-standard bus interfaces (PCIe, Ethernet, GEPON, USB, DDR3, etc.) is a plus.
• Familiarity with scripting languages such as TCL, Perl, Python
• Strong analytical and problem-solving skills
• Excellent written and verbal communications skills
• A self-motivated team player