As a member of physical implementation team, the candidate is responsible for SoC physical implementation using automatic place and route EDA tools. 
 
-Work with digital frontend design team to complete SoC physical implementation
 
-          Physical implementation including but not limited to floorplanning, power plan synthesis and analysis, timing optimization and closure, CTS, routing and post-routing optimization
-          Physical verification including DRC, LVS, IR drop, EM, and ESD
 
Requirement
-          Expertise in APR, physical implementation, low power design both block level and chip top
-          Able to use industry standard APR EDA tools, Synopsys and Cadence
-          Fluency in tcl/perl/shell script
-          Effective communication skill, both verbal and written, Mandarin Chinese and English
-          Ability to think and work independently with different teams
-          Interested in APR flow enhancement
-          Tapeout experience with advanced process node ( <14nm) is a plus
-          Experience with hierarchical, chip top implementation would be added advantage