As a member of DFT engineering team, the candidate will develop methodologies and implement DFT for pre/post-silicon DFT flow.
- Work with digital design team and PD to meet low cost and high quality testing
-Define DFT plan and execute DFT/ATPG tasks
- Block level and top level DFT implementation
- Co-work with RTL design to implement DFT circuit
- DFT architecture enhancement
- ATPG pattern simulation
 
Requirement
-          Expertise in DFT architecture, including scan, mbist, at-speed, scan compression, IP testing
-          Able to use industry standard DFT EDA tools, Synopsys/Mentor DFT/ATPG tools
-          Fluency in tcl/perl/shell script
-          Memory BIST and RTL design experience are plus
-          Effective communication skill, both verbal and written, Mandarin Chinese and English
-          Ability to think and work independently with different teams
-          Interested in DFT/ATPG innovation and flow enhancement
-          Tapeout experience with advanced process node ( <14nm) is a plus
-          Experience with hierarchical, chip top DFT implementation would be added advantage