Responsibilities:
1.Responsible for SDC and UPF/CPF development and debug.
2.Focus on design floor planning, power planning, IO planning, placement & CTS and routing, handling timing and congestion issue during project implementation.
3.IP level and chip level physical verification and DFM rule checking.
4.Power analysis and IR drop/EM analysis for both static and dynamic.
5.Strong capability in timing analysis, and independently handle all timing issues from netlist/RTL to GDS process.
6.Responsible for timing signoff for all functional modes and concerns, and work closely with DFT engineer for scan modes timing closure.
7.Work closely with package team and IO team regarding IO placement to address IO ESD, SSO and chip power supplement concerns.
8.Communicate with customer as well as AE or sales.
 
Requirements:
1.Bachelor’s degree or above in EE.
2.Skilled in csh/perl/tcl.
3.2+ years work experience in relevant areas is required for Senior Engineer position.
4.Good knowledge in at least one of the following disciplines: high speed chip P&R skills, advance node chip P&R, hierarchical flow or low power P&R implementation, physical layout & verification.
 
5. Rich experience on timing/noise violation fixing and CTS tree synthesis.
 
6. Good understanding about entire development flow of IC design.
 
7. Good understanding about FE design, process, package, testing, etc.
 
8. Fluent in both English and Chinese.
 
9. Self motivated, good communication skill and team work spirit.