Job description:

Be responsible for DFT implementation, verification, DFT structure and test plan definition
Silicon bring up, pattern tuning
DFT flow development and benchmark
Support DFT timing closure and related design rule check
Silicon debug and yield improvement

任職要求：
1. BS or MS, major in EE or related discipline
2. Solid background on Verilog and ASIC design
3. Proven knowledge and expertise in defining and implementing IO test, Scan test plans and ATPG, understanding on Memory BIST, be familiar with Mentor/synopsys/Cadence EDA tools
4. Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
5. Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools
6. Experience in silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing and diagnostics
7. Programming and scripting skills in Perl, or Tcl
8. Good communication capability and teamwork spirit
9. Strong and continues learning capability, self motivated