Responsibilities:
1.Porting ASIC to FPGA
2. Generate/run/debug test cases on FPGA
3. FPGA High-speed solution, including RTL coding, IP using, simulation, timing closure and bit file generation
4. Work with SoC team and software team on FPGA debug
 
Requirements:
1.Bachelor degree or above in EE, CS or Automation
2.with 2+ years of work experience with FPGA
3.More experience in FPGA IP using/debug, such as DCM/PLL, Memory, PCIe, DDR3/DDR4 interface etc
4. Familiar with FPGA design/simulation flow using Verilog and EDA tools such as Xilinx ISE/Vivado
5.Fluent in both English and Chinese
6.Good problem solving and design document skill
7.Self motivated, good communication skill and team work spirit
 
 
職位描述：

1. 完成RTL從ASIC到FPGA的移植
2. 產(chǎn)生FPGA仿真和測(cè)試case
3. 完成FPGA的高速資源搭建，包括RTL設(shè)計(jì)，IP使用，仿真，時(shí)序收斂和bit文件生成
4. 協(xié)同SoC工程師和軟件工程師完成FPGA的功能調(diào)試

1. 電子，信電，自動(dòng)化及相關(guān)專業(yè)的碩士或者博士
2. 2年以上FPGA開(kāi)發(fā)經(jīng)驗(yàn)
3. 有FPGA 內(nèi)部DCM/PLL, memory, PCIe, DDR3/DDR4 資源的使用和開(kāi)發(fā)經(jīng)驗(yàn)
4. 熟悉FPGA開(kāi)發(fā)及仿真流程和相關(guān)的xilinx工具，如ISE/Vivado.
5. 能熟練用中英文溝通
6. 有較強(qiáng)的技術(shù)問(wèn)題解決能力和文檔編寫(xiě)能力
7. 有較強(qiáng)的自我驅(qū)動(dòng)能力，良好的溝通和團(tuán)隊(duì)合作能力