Responsibilities:
1. Comprehend the SoC clock structure and working mode and prepare the SDC file for SoC design.
2. Prepare the DFT plan for the SoC design.
3. SCAN/MBIST/BSD insertion and synthesize methodology for Flatten/ Hierarchical design.
4. Pre/Post simulation for test patterns.
5. Cooperate with timing engineer for timing signoff (STA).
6. Analog IP test implementation and simulation.
7. Support ATE engineer for chip testing debug, and analyze ATE log file to locate root cause of failure.
8. Formal check of RTL and netlist.
 
Requirements:
1. Bachelor's degree or above, major in EE, CS or relevant.
2. Above 5 years work experience to the one with Bachelor's degree and above 3 years with Master's degree is required for Senior Engineer position.
3. Skilled in SoC PPA, better for low power design.
4. Improve low test coverage to achieve higher coverage.
5. Skilled in csh/perl/tcl scripts.
6. Be familiar with concept of SoC and P&R physical implementation.
7. Fluent in both English and Chinese.
8. Good team work spirit