VLSI Physical Design 部門成立于 2005 年， 在過去的 16 年里，我們成功地參與并設計了 NVIDIA 發(fā)布的所有產(chǎn)品。我們使用了前沿領先的生產(chǎn)工藝、EDA 工具以及最復雜的設計流程。致力于先進的產(chǎn)品設計，挑戰(zhàn)技術之巔是我們一貫的追求。

【未來，你將在這些方面施展才華】
負責 NVIDIA 公司所有芯片（包括 GeForce，Tegra，Tesla，Quadro 等系列）的物理設計及其實現(xiàn)（Netlist to GDSII）， 以及流程開發(fā)（Flow development）。
致力于：
-芯片規(guī)劃及布局, 頂層設計到底層模塊的劃分
-電源 / 時鐘分布及規(guī)劃
-布局布線 (包含從頂層設計以及底層模塊的全部內容)
-靜態(tài)時序 / 功耗 / 噪聲 / 可制造性優(yōu)化及分析
-物理驗證
-流程自動化以及回歸測試
-與 EDA 提供商合作進行工具評估和改進
-開發(fā)內部工具和解決方案

【我們期待這樣的你】
-有數(shù)字芯片后端設計相關工作經(jīng)驗
-有 EDA 工具使用經(jīng)驗 Synopsys （ICC2 / DC / PT / STAR - RC), Cadence (EDI / Innovus/ Voltus) or Ansys (Redhawk)
-有如下工作經(jīng)驗 Floorplanning, P&R, Timing closure, Power / Clock analysis
-有芯片物理驗證相關經(jīng)驗
-有使用 Perl，Tcl，Python 和 Shell 等語言編寫腳本的能力優(yōu)先

Job Description
We are now looking for a Physical Design Engineer. VLSI Physical Design Team at NVIDIA Shanghai has been built up since 2005. The team has made contribution to various successful products launched by NVIDIA Corporation over 15 years. We utilize latest process technology, advanced EDA tools, and sophisticated design methodology. We always work on the most challenging designs, and push for performance limit.

What you’ll be doing:
A senior role in physical design for NVIDIA GPU and Mobile chips Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation.

What we need to see: 
• BS in Engineering or Science or equivalent experience.
• Power user of EDA tools from Synopsys (ICC2/DC/PT/STAR-RC),Cadence (EDI/Innovus/Voltus) or Mentor (Olympus-SOC).
• Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on advanced technology nodes.
Ways to stand out from the crowd: 
• MS in Engineering or Science.
• Knowledge in FinFET technology, circuit design, and package design.
• Experience in physical verification tools from Synopsys (ICV) or Mentor (Calibre).
• Proficiency in Perl, Python, TCL and Makefile scripts.